Designed for nanometer-scale silicon ICs, a new wire-bond chip-packaging process–called Pad on I/O–by chip manufacturer LSI Logic (Milpitas, CA) places bond pads directly on active copper/low-K ...

Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps ...

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid ...

The semiconductor equipment industry has witnessed a gradual increase in the proportion of packaging and testing equipment, with the continuous advancement of advanced packaging. Die bonding plays a ...