Semiconductor Engineering

Raising The Bar On Flat CDC Verification With Hierarchical Data Models

Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number ...
Semiconductor Engineering

Comprehensive CDC Verification Using Advanced Hierarchical Data Models

In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model ...
Nature

Analyzing 'omics data using hierarchical models

Interpreting 'omics data often involves statistical analysis of large numbers of loci such as genes, binding sites or single-nucleotide polymorphisms (SNPs). Although the data set as a whole may be ...
EDN

ATopTech Introduces Industry’s First Top-Level Design Tool to Seamlessly Integrate All Hierarchical Functions with Block-Level Implementation

San Francisco, CA – July 27, 2009 — ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and ...
Electronic Design

Hierarchy Spells Order For SoC Data-Management Tool

No longer must SoC designers struggle with data that's organized in a file-based fashion. Increasingly, system-on-a-chip (SoC) design is a discipline that requires its practitioners to look, at least ...