A technical paper titled “Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS” was just published by researchers at Anhui University, Hefei University of ...
Semiconductor manufacturers rely on latch-up tests to characterize ICs for susceptibility to electrical failure. Engineers can use various methods to perform latch-up tests, but the only standard that ...
The effects of cosmic rays were once discussed in “Doubled-up MOSFETs“. The idea was that component redundancy, paired MOSFETs in that case, would allow one MOSFET to still function even if its ...
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