Design-Reuse

PLDA demonstrates successful PCIe 5.0 Link Training at 32 GT/s with its PCIe 5.0 controller and Broadcom PHY

SAN JOSE, Calif. October 22, 2020 -- PLDA, the industry leader in PCI Express® controller IP solutions has today unveiled their PCIe 5.0 demonstration. The demo showcases stable PCIe 5.0 Link Training ...
Electronic Design

How PCIe Tech Can Help Build Machine-Learning Accelerators

How to build an ML accelerator chip using PCI Express. What is the training process for a machine-learning model? The emergence of complex models that need multiple accelerators. Machine-learning (ML) ...
Semiconductor Engineering

Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers

In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for ...
Semiconductor Engineering

An Overview Of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature ...
Electronic Design

Keeping Up With PCIe 3.0 Test Requirements Part 1

With the release of new and improved specifications for SATA, USB, and now PCI Express (PCIe), the era of third-generation (Gen3) serial data has arrived. Not only are the new specifications faster, ...