EDN

Commentary: SystemVerilog enables design with verification

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...
EDN

What SystemVerilog adds

SystemVerilog was developed as an extension to the widely used Verilog hardware description language. In addition to new design constructs that bring the language to a higher level of abstraction, it ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Electronic Design

Functional Verification Tool Gains Link To SystemVerilog Assertions

With the addition of a standard assertion-language link, the 360 Module Verifier (360 MV), a functional verification environment, is equipped to fully leverage both SystemVerilog assertions and Open ...