All
Search
Images
Videos
Shorts
Maps
News
More
Shopping
Flights
Travel
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
Timing Analysis in VLSI | STA - timing paths explained | STA Ep. 0
…
20.1K views
1 month ago
linkedin.com
Timing Arc
Sep 13, 2016
vlsi-expert.com
0:37
Discover how InspireSemi successfully taped out their Thun
…
34.1K views
Dec 3, 2024
Facebook
Cadence India
Digital Timing Basics for VLSI Interview & SoC Design
Aug 7, 2023
git.ir
Static Timing Analysis using Cadence Tempus - Digital System
…
Jun 30, 2020
digitalsystemdesign.in
ETM (Extracted Timing Models) basics
Feb 7, 2011
vlsi-expert.com
0:44
1.2K views · 11 reactions | As the industry leader in aging-aware ST
…
2K views
1 month ago
Facebook
Cadence
Path Base Analysis (PBA) Vs Graph Base Analysis (GBA) - part1
Nov 7, 2017
vlsi-expert.com
10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (
…
Jan 10, 2014
vlsi-expert.com
0:07
18.What are setup and hold margins
5 views
1 month ago
YouTube
Maharshi Sanand Yadav T
7:32
D-flipflip on Cadence Virtuoso Report - VLSI HCMUTE - Hoang M
…
9 views
3 months ago
YouTube
Anh Ba
0:17
14.What is the difference between pessimism and optimism in STA
10 views
1 month ago
YouTube
Maharshi Sanand Yadav T
0:10
16.What is max transition and max capacitance
6 views
1 month ago
YouTube
Maharshi Sanand Yadav T
1:01
2.What is a timing path, and what are its components
1 views
3 months ago
YouTube
Maharshi Sanand Yadav T
4:16
Source Insertion Delay | CTS | Physical Design | VLSI
2 views
5 days ago
YouTube
Back To Basics
0:34
Setup & Hold Time | Why Chips Fail Even with Correct Code ?#vlsi#tim
…
104 views
1 month ago
YouTube
Silicon Simplified
0:30
VLSI Job Alert! 🚀 Capgemini Hiring PD/STA Engineers in Bengaluru #
…
1 month ago
YouTube
VLSI Job Updates
0:26
create_clock | example 5 | sdc constraints | synthesis | STA #sta
…
286 views
2 months ago
YouTube
Maharshi Sanand Yadav T
Mastering STA Commands and Timing Report Analysis in Static T
…
2.3K views
Jun 19, 2021
YouTube
TechSimplified TV
Practical Guide to Hands-On Static Timing Analysis with Open Timer
…
2.5K views
Jun 26, 2021
YouTube
TechSimplified TV
False Path in VLSI | Examples of false path | Write false path constr
…
17.3K views
Aug 7, 2020
YouTube
Team VLSI
VLSI | Setup Time | Hold Time | Static Timing Analysis (STA) | Digi
…
4.1K views
Sep 17, 2020
YouTube
Mahendra Maram World
Importance of get_timing_paths command in Prime Time with a ex
…
2.3K views
Jul 17, 2019
YouTube
VLSI Physical Design
30:43
Static Timing Analysis (STA)
16.3K views
Sep 29, 2020
YouTube
Feroz Chaudhary
3:50
VLSI : Synthesis flow
19.8K views
Jul 29, 2020
YouTube
Feroz Chaudhary
21:34
VLSI Physical Design using Cadence Tools
50.5K views
May 18, 2016
YouTube
Study Materials
20:21
Introduction to SDC Timing Constraints
25.3K views
May 25, 2021
YouTube
Cadence Design Systems
29:41
Understanding Timing Analysis in FPGAs
35.1K views
Mar 9, 2021
YouTube
Altera
11:09
STA_L1c Overview of VLSI Backend Design Flow
14K views
Oct 14, 2018
YouTube
VLSI EXPERT (vlsi EG)
3:59
Tempus est Iocundum "Codex Buranus, 179"
2.7M views
Aug 20, 2010
YouTube
sh4m69
See more videos
More like this
Feedback